Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 5/15 and 4096-symbol mapping, and bit interleaving method using same

ABSTRACT

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 5/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 4096-symbol mapping.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of Korean Patent Application Nos.10-2014-0036153 and 10-2015-0023417, filed Mar. 27, 2014 and Feb. 16,2015, respectively, which are hereby incorporated by reference herein intheir entirety.

BACKGROUND 1. Technical Field

The present disclosure relates generally to an interleaver and, moreparticularly, to a bit interleaver that is capable of distributing bursterrors occurring in a digital broadcast channel.

2. Description of the Related Art

Bit-Interleaved Coded Modulation (BICM) is bandwidth-efficienttransmission technology, and is implemented in such a manner that anerror-correction coder, a bit-by-bit interleaver and a high-ordermodulator are combined with one another.

BICM can provide excellent performance using a simple structure becauseit uses a low-density parity check (LDPC) coder or a Turbo coder as theerror-correction coder. Furthermore, BICM can provide high-levelflexibility because it can select modulation order and the length andcode rate of an error correction code in various forms. Due to theseadvantages, BICM has been used in broadcasting standards, such as DVB-T2and DVB-NGH, and has a strong possibility of being used in othernext-generation broadcasting systems.

However, in spite of those advantages, BICM suffers from the rapiddegradation of performance unless burst errors occurring in a channelare appropriately distributed via the bit-by-bit interleaver.Accordingly, the bit-by-bit interleaver used in BICM should be designedto be optimized for the modulation order or the length and code rate ofthe error correction code.

SUMMARY

At least one embodiment of the present invention is directed to theprovision of an intra-BICM bit interleaver that can effectivelydistribute burst errors occurring in a broadcasting system channel.

At least one embodiment of the present invention is directed to theprovision of a bit interleaver that is optimized for an LDPC coderhaving a length of 64800 and a code rate of 5/15 and a modulatorperforming 4096-symbol mapping and, thus, can be applied tonext-generation broadcasting systems, such as ATSC 3.0.

In accordance with an aspect of the present invention, there is provideda bit interleaver, including a first memory configured to store alow-density parity check (LDPC) codeword having a length of 64800 and acode rate of 5/15; a processor configured to generate an interleavedcodeword by interleaving the LDPC codeword on a bit group basis, thesize of the bit group corresponding to a parallel factor of the LDPCcodeword; and a second memory configured to provide the interleavedcodeword to a modulator for 4096-symbol mapping.

The 4096-symbol mapping may be NUC (Non-Uniform Constellation) symbolmapping corresponding to 4096 constellations (symbols).

The parallel factor may be 360, and each of the bit groups may include360 bits.

The LDPC codeword may be represented by (u₀, u₁, . . . , u_(N) _(ldpc)⁻¹) (where N_(ldpc is)64800), and may be divided into 180 bit groupseach including 360 bits, as in the following equation:X _(j) ={u _(k)|360×j≤k<360×(j+1), 0≤k<N _(ldpc)} for 0≤j<N _(group)where X_(j) is an j-th bit group, N_(ldpc) is 64800, and N_(group) is180.

The interleaving may be performed using the following equation usingpermutation order:Y _(j) =X _(π(j)) 0≤j≤N _(group)where X_(j) is the j-th bit group, Y_(j) is an interleaved j-th bitgroup, and π(j) is a permutation order for bit group-based interleaving(bit group-unit interleaving).

The permutation order may correspond to an interleaving sequencerepresented by the following equation:interleaving sequence={146 89 57 16 164 138 91 78 90 66 122 12 9 157 1468 112 128 74 45 28 87 158 56 61 168 18 161 95 99 139 22 65 130 166 118150 49 142 44 36 1 121 6 46 29 88 47 0 58 105 43 80 64 107 21 55 151 8145 163 7 98 123 17 11 153 136 52 3 13 34 160 102 125 114 152 84 32 9733 60 62 79 37 129 38 165 71 75 59 144 127 132 104 53 162 103 120 54 155116 48 77 76 73 113 119 179 177 41 19 92 109 31 143 178 108 39 140 10640 5 25 81 176 101 124 126 72 111 4 173 156 134 86 174 2 170 35 175 13715 24 69 96 30 117 67 171 149 169 63 23 20 167 27 147 51 10 82 131 85110 94 135 172 148 50 154 42 70 115 26 83 141 100 133 93 159}

In accordance with another aspect of the present invention, there isprovided a bit interleaving method, including storing an LDPC codewordhaving a length of 64800 and a code rate of 5/15; generating aninterleaved codeword by interleaving the LDPC codeword on a bit groupbasis corresponding to the parallel factor of the LDPC codeword; andoutputting the interleaved codeword to a modulator for 4096-symbolmapping.

In accordance with still another aspect of the present invention, thereis provided a BICM device, including an error-correction coderconfigured to output an LDPC codeword having a length of 64800 and acode rate of 5/15; a bit interleaver configured to interleave the LDPCcodeword on a bit group basis corresponding to the parallel factor ofthe LDPC codeword and output the interleaved codeword; and a modulatorconfigured to perform 4096-symbol mapping on the interleaved codeword.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, features and advantages of the presentinvention will be more clearly understood from the following detaileddescription taken in conjunction with the accompanying drawings, inwhich:

FIG. 1 is a block diagram illustrating a broadcast signal transmissionand reception system according to an embodiment of the presentinvention;

FIG. 2 is an operation flowchart illustrating a broadcast signaltransmission and reception method according to an embodiment of thepresent invention;

FIG. 3 is a diagram illustrating the structure of a parity check matrix(PCM) corresponding to an LDPC code to according to an embodiment of thepresent invention;

FIG. 4 is a diagram illustrating the bit groups of an LDPC codewordhaving a length of 64800;

FIG. 5 is a diagram illustrating the bit groups of an LDPC codewordhaving a length of 16200;

FIG. 6 is a diagram illustrating interleaving that is performed on a bitgroup basis in accordance with an interleaving sequence;

FIG. 7 is a block diagram illustrating a bit interleaver according to anembodiment of the present invention; and

FIG. 8 is an operation flowchart illustrating a bit interleaving methodaccording to an embodiment of the present invention.

DETAILED DESCRIPTION

Embodiments of the present invention will be described in detail belowwith reference to the accompanying drawings. Repeated descriptions anddescriptions of well-known functions and configurations that have beendeemed to make the gist of the present invention unnecessarily obscurewill be omitted below. The embodiments of the present invention areintended to fully describe the present invention to persons havingordinary knowledge in the art to which the present invention pertains.Accordingly, the shapes, sizes, etc. of components in the drawings maybe exaggerated to make the description obvious.

Embodiments of the present invention will be described in detail belowwith reference to the accompanying drawings.

FIG. 1 is a block diagram illustrating a broadcast signal transmissionand reception system according to an embodiment of the presentinvention.

Referring to FIG. 1, it can be seen that a BICM device 10 and a BICMreception device 30 communicate with each other over a wireless channel20.

The BICM device 10 generates an n-bit codeword by encoding k informationbits 11 using an error-correction coder 13. In this case, theerror-correction coder 13 may be an LDPC coder or a Turbo coder.

The codeword is interleaved by a bit interleaver 14, and thus theinterleaved codeword is generated.

In this case, the interleaving may be performed on a bit group basis (bya unit of a bit group). In this case, the error-correction coder 13 maybe an LDPC coder having a length of 64800 and a code rate of 5/15. Acodeword having a length of 64800 may be divided into a total of 180 bitgroups. Each of the bit groups may include 360 bits, i.e., the parallelfactor of an LDPC codeword.

In this case, the interleaving may be performed on a bit group basis (bya unit of a bit group) in accordance with an interleaving sequence,which will be described later.

In this case, the bit interleaver 14 prevents the performance of errorcorrection code from being degraded by effectively distributing bursterrors occurring in a channel. In this case, the bit interleaver 14 maybe separately designed in accordance with the length and code rate ofthe error correction code and the modulation order.

The interleaved codeword is modulated by a modulator 15, and is thentransmitted via an antenna 17.

In this case, the modulator 15 may be based on a concept includingsymbol mapper (symbol mapping device). In this case, the modulator 15may be a symbol mapping device performing 4096-symbol mapping which mapscodes onto 4096 constellations (symbols).

In this case, the modulator 15 may be a uniform modulator, such as aquadrature amplitude modulation (QAM) modulator, or a non-uniformmodulator.

The modulator 15 may be a symbol mapping device performing NUC(Non-Uniform Constellation) symbol mapping which uses 4096constellations (symbols).

The signal transmitted via the wireless channel 20 is received via theantenna 31 of the BICM reception device 30, and, in the BICM receptiondevice 30, is subjected to a process reverse to the process in the BICMdevice 10. That is, the received data is demodulated by a demodulator33, is deinterleaved by a bit deinterleaver 34, and is then decoded byan error correction decoder 35, thereby finally restoring theinformation bits.

It will be apparent to those skilled in the art that the above-describedtransmission and reception processes have been described within aminimum range required for a description of the features of the presentinvention and various processes required for data transmission may beadded.

FIG. 2 is an operation flowchart illustrating a broadcast signaltransmission and reception method according to an embodiment of thepresent invention.

Referring to FIG. 2, in the broadcast signal transmission and receptionmethod according to this embodiment of the present invention, input bits(information bits) are subjected to error-correction coding at stepS210.

That is, at step S210, an n-bit codeword is generated by encoding kinformation bits using the error-correction coder.

In this case, step S210 may be performed as in an LDPC encoding method,which will be described later.

Furthermore, in the broadcast signal transmission and reception method,an interleaved codeword is generated by interleaving the n-bit codewordon a bit group basis at step S220.

In this case, the n-bit codeword may be an LDPC codeword having a lengthof 64800 and a code rate of 5/15. The codeword having a length of 64800may be divided into a total of 180 bit groups. Each of the bit groupsmay include 360 bits corresponding to the parallel factors of an LDPCcodeword.

In this case, the interleaving may be performed on a bit group basis (bya unit of a bit group) in accordance with an interleaving sequence,which will be described later.

Furthermore, in the broadcast signal transmission and reception method,the encoded data is modulated at step S230.

That is, at step S230, the interleaved codeword is modulated using themodulator.

In this case, the modulator may be based on a concept including symbolmapper (symbol mapping device). In this case, the modulator may be asymbol mapping device performing 4096-symbol mapping which maps codesonto 4096 constellations (symbols).

In this case, the modulator may be a uniform modulator, such as a QAMmodulator, or a non-uniform modulator.

The modulator may be a symbol mapping device performing NUC (Non-UniformConstellation) symbol mapping which uses 4096 constellations (symbols).

Furthermore, in the broadcast signal transmission and reception method,the modulated data is transmitted at step S240.

That is, at step S240, the modulated codeword is transmitted over thewireless channel via the antenna.

Furthermore, in the broadcast signal transmission and reception method,the received data is demodulated at step S250.

That is, at step S250, the signal transmitted over the wireless channelis received via the antenna of the receiver, and the received data isdemodulated using the demodulator.

Furthermore, in the broadcast signal transmission and reception method,the demodulated data is deinterleaved at step S260. In this case, thedeinterleaving of step S260 may be reverse to the operation of stepS220.

Furthermore, in the broadcast signal transmission and reception method,the deinterleaved codeword is subjected to error correction decoding atstep S270.

That is, at step S270, the information bits are finally restored byperforming error correction decoding using the error correction decoderof the receiver.

In this case, step S270 corresponds to a process reverse to that of anLDPC encoding method, which will be described later.

An LDPC code is known as a code very close to the Shannon limit for anadditive white Gaussian noise (AWGN) channel, and has the advantages ofasymptotically excellent performance and parallelizable decodingcompared to a turbo code.

Generally, an LDPC code is defined by a low-density parity check matrix(PCM) that is randomly generated. However, a randomly generated LDPCcode requires a large amount of memory to store a PCM, and requires alot of time to access memory. In order to overcome these problems, aquasi-cyclic LDPC (QC-LDPC) code has been proposed. A QC-LDPC code thatis composed of a zero matrix or a circulant permutation matrix (CPM) isdefined by a PCM that is expressed by the following Equation 1:

$\begin{matrix}{{H = \begin{bmatrix}J^{a_{11}} & J^{a_{12}} & \ldots & J^{a_{1n}} \\J^{a_{21}} & J^{a_{22}} & \ldots & J^{a_{2n}} \\\vdots & \vdots & \ddots & \vdots \\J^{a_{m\; 1}} & J^{a_{m\; 2}} & \ldots & J^{a_{mn}}\end{bmatrix}},{{{for}\mspace{14mu} a_{ij}} \in \left\{ {0,1,\ldots\;,{L - 1},\infty} \right\}}} & (1)\end{matrix}$

In this equation, J is a CPM having a size of L×L, and is given as thefollowing Equation 2. In the following description, L may be 360.

$\begin{matrix}{J_{L \times L} = \begin{bmatrix}0 & 1 & 0 & \ldots & 0 \\0 & 0 & 1 & \ldots & 0 \\\vdots & \vdots & \vdots & \ddots & \vdots \\0 & 0 & 0 & \ldots & 1 \\1 & 0 & 0 & \ldots & 0\end{bmatrix}} & (2)\end{matrix}$

Furthermore, J^(i) is obtained by shifting an L×L identity matrix I (J⁰)to the right i (0≤i<L) times, and J^(∞) is an L×L zero matrix.Accordingly, in the case of a QC-LDPC code, it is sufficient if onlyindex exponent i is stored in order to store J^(i), and thus the amountof memory required to store a PCM is considerably reduced.

FIG. 3 is a diagram illustrating the structure of a PCM corresponding toan LDPC code to according to an embodiment of the present invention.

Referring to FIG. 3, the sizes of matrices A and C are g×K and(N−K−g)×(K+g), respectively, and are composed of an L×L zero matrix anda CPM, respectively. Furthermore, matrix Z is a zero matrix having asize of g×(N−−g), matrix D is an identity matrix having a size of(N−K−g)×(N−K−g), and matrix B is a dual diagonal matrix having a size ofg×g. In this case, the matrix B may be a matrix in which all elementsexcept elements along a diagonal line and neighboring elements below thediagonal line are 0, and may be defined as the following Equation 3:

$\begin{matrix}{B_{g \times g} = \begin{bmatrix}I_{L \times L} & 0 & 0 & \ldots & 0 & 0 & 0 \\I_{L \times L} & I_{L \times L} & 0 & \ldots & 0 & 0 & 0 \\0 & I_{L \times L} & I_{L \times L} & \vdots & 0 & 0 & 0 \\\vdots & \vdots & \vdots & \ddots & \vdots & \vdots & \vdots \\0 & 0 & 0 & \ldots & I_{L \times L} & I_{L \times L} & 0 \\0 & 0 & 0 & \ldots & 0 & I_{L \times L} & I_{L \times L}\end{bmatrix}} & (3)\end{matrix}$where I_(L×L) is an identity matrix having a size of L×L.

That is, the matrix B may be a bit-wise dual diagonal matrix, or may bea block-wise dual diagonal matrix having identity matrices as itsblocks, as indicated by Equation 3. The bit-wise dual diagonal matrix isdisclosed in detail in Korean Patent Application Publication No.2007-0058438, etc.

In particular, it will be apparent to those skilled in the art that whenthe matrix B is a bit-wise dual diagonal matrix, it is possible toperform conversion into a Quasi-cyclic form by applying row or columnpermutation to a PCM including the matrix B and having a structureillustrated in FIG. 3.

In this case, N is the length of a codeword, and K is the length ofinformation.

The present invention proposes a newly designed QC-LDPC code in whichthe code rate thereof is 5/15 and the length of a codeword is 64800, asillustrated in the following Table 1. That is, the present inventionproposes an LDPC code that is designed to receive information having alength of 21600 and generate an LDPC codeword having a length of 64800.

Table 1 illustrates the sizes of the matrices A, B, C, D and Z of theQC-LDPC code according to the present invention:

TABLE 1 Sizes Code rate Length A B C D Z 5/15 64800 1440 × 1440 × 41760× 41760 × 1080 × 21600 1440 23040 41760 41760

The newly designed LDPC code may be represented in the form of asequence (progression), an equivalent relationship is establishedbetween the sequence and matrix (parity bit check matrix), and thesequence may be represented, as follows:

Sequence Table 1st row: 221 1011 1218 4299 7143 8728 11072 15533 1735633909 36833 2nd row: 360 1210 1375 2313 3493 16822 21373 23588 2365626267 34098 3rd row: 544 1347 1433 2457 9186 10945 13583 14858 1919534606 37441 4th row: 37 596 715 4134 8091 12106 24307 24658 34108 4059142883 5th row: 235 398 1204 2075 6742 11670 13512 23231 24784 2791534752 6th row: 204 873 890 13550 16570 19774 34012 35249 37655 3988542890 7th row: 221 371 514 11984 14972 15690 28827 29069 30531 3101843121 8th row: 280 549 1435 1889 3310 10234 11575 15243 20748 3046936005 9th row: 223 666 1248 13304 14433 14732 18943 21248 23127 3852939272 10th row: 370 819 1065 9461 10319 25294 31958 33542 37458 3968140039 11st row: 585 870 1028 5087 5216 12228 16216 16381 16937 2713227893 12nd row: 164 167 1210 7386 11151 20413 22713 23134 24188 3677138992 13rd row: 298 511 809 4620 7347 8873 19602 24162 29198 34304 4114514th row: 105 830 1212 2415 14759 15440 16361 16748 22123 32684 4257515th row: 659 665 668 6458 22130 25972 30697 31074 32048 36078 3712916th row: 91 808 953 8015 8988 13492 13987 15979 28355 34509 39698 17throw: 594 983 1265 3028 4029 9366 11069 11512 27066 40939 41639 18th row:506 740 1321 1484 10747 16376 17384 20285 31502 38925 42606 19th row:338 356 975 2022 3578 18689 18772 19826 22914 24733 27431 20th row: 7091264 1366 4617 8893 25226 27800 29080 30277 37781 39644 21st row: 8401179 1338 2973 3541 7043 12712 15005 17149 19910 36795 22nd row: 10091267 1380 4919 12679 22889 29638 30987 34637 36232 37284 23rd row: 466913 1247 1646 3049 5924 9014 20539 34546 35029 36540 24th row: 374 697984 1654 5870 10883 11684 20294 28888 31612 34031 25th row: 117 240 6355093 8673 11323 12456 14145 21397 39619 42559 26th row: 122 1265 142713528 14282 15241 16852 17227 34723 36836 39791 27th row: 595 1180 13106952 17916 24725 24971 27243 29555 32138 35987 28th row: 140 470 101713222 13253 18462 20806 21117 28673 31598 37235 29th row: 7 710 10728014 10804 13303 14292 16690 26676 36443 41966 30th row: 48 189 75912438 14523 16388 23178 27315 28656 29111 29694 31st row: 285 387 4104294 4467 5949 25386 27898 34880 41169 42614 32nd row: 474 545 132010506 13186 18126 27110 31498 35353 36193 37322 33rd row: 1075 1130 142411390 13312 14161 16927 25071 25844 34287 38151 34th row: 161 396 4275944 17281 22201 25218 30143 35566 38261 42513 35th row: 233 247 6941446 3180 3507 9069 20764 21940 33422 39358 36th row: 271 508 1013 627121760 21858 24887 29808 31099 35475 39924 37th row: 8 674 1329 3135 511014460 28108 28388 31043 31137 31863 38th row: 1035 1222 1409 8287 1608324450 24888 29356 30329 37834 39684 39th row: 391 1090 1128 1866 409510643 13121 14499 20056 22195 30593 40th row: 55 161 1402 6289 6837 879117937 21425 26602 30461 37241 41st row: 110 377 1228 6875 13253 1703219008 23274 32285 33452 41630 42nd row: 360 638 1355 5933 12593 1353323377 23881 24586 26040 41663 43rd row: 535 1240 1333 3354 10860 1603232573 34908 34957 39255 40759 44th row: 526 936 1321 7992 10260 1852728248 29356 32636 34666 35552 45th row: 336 785 875 7530 13062 1307518925 27963 28703 33688 36502 46th row: 36 591 1062 1518 3821 7048 1119717781 19408 22731 24783 47th row: 214 1145 1223 1546 9475 11170 1606121273 38688 40051 42479 48th row: 1136 1226 1423 20227 22573 24951 2646229586 34915 42441 43048 49th row: 26 276 1425 6048 7224 7917 8747 2755928515 35002 37649 50th row: 127 294 437 4029 8585 9647 11904 24115 2851436893 39722 51st row: 748 1093 1403 9536 19305 20468 31049 38667 4050240720 41949 52nd row: 96 638 743 9806 12101 17751 22732 24937 3200732594 38504 53rd row: 649 904 1079 2770 3337 9158 20125 24619 3292133698 35173 54th row: 401 518 984 7372 12438 12582 18704 35874 3942039503 39790 55th row: 10 451 1077 8078 16320 17409 25807 28814 3061341261 42955 56th row: 405 592 1178 15936 18418 19585 21966 24219 3063734536 37838 57th row: 50 584 851 9720 11919 22544 22545 25851 3556741587 41876 58th row: 911 1113 1176 1806 10058 10809 14220 19044 2074829424 36671 59th row: 441 550 1135 1956 11254 18699 30249 33099 3458735243 39952 60th row: 510 1016 1281 8621 13467 13780 15170 16289 2092526426 34479 61st row: 4969 5223 17117 21950 22144 24043 27151 39809 62ndrow: 11452 13622 18918 19670 23995 32647 37200 37399 63rd row: 6351 642613185 13973 16699 22524 31070 31916 64th row: 4098 10617 14854 1800428580 36158 37500 38552

An LDPC code that is represented in the form of a sequence is beingwidely used in the DVB standard.

According to an embodiment of the present invention, an LDPC codepresented in the form of a sequence is encoded, as follows. It isassumed that there is an information block S=(s₀, s₁, . . . , s_(K−1))having an information size K. The LDPC encoder generates a codewordΛ=(λ₀, λ₁, λ₂, . . . , λ_(N−1)) having a size of N=K+M₁+M₂ using theinformation block S having a size K. In this case, M₁=g, and M₂=N−K−g.Furthermore, M₁ is the size of parity bits corresponding to the dualdiagonal matrix B, and M₂ is the size of parity bits corresponding tothe identity matrix D. The encoding process is performed, as follows:

Initialization:λ_(i) =s _(i) for i=0,1, . . . ,K−1  (4)p _(j)=0 for j=0,1, . . . ,M ₁ +M ₂−1

First information bit λ₀ is accumulated at parity bit addressesspecified in the 1st row of the sequence of the Sequence Table. Forexample, in an LDPC code having a length of 64800 and a code rate of5/15, an accumulation process is as follows:p ₂₂₁ =p ₂₂₁⊕λ₀ p ₁₀₁₁ =p ₁₀₁₁⊕λ₀ p ₁₂₁₈ =p ₁₂₁₈⊕λ₀ p ₄₂₉₉ =p ₄₂₉₉⊕λ₀ p₇₁₄₃ =p ₇₁₄₃⊕λ₀ p ₈₇₂₈ =p ₈₇₂₈⊕λ₀ p ₁₁₀₇₂ =p ₁₁₀₇₂⊕λ₀ p ₁₅₅₃₃ =p₁₅₅₃₃⊕λ₀ p ₁₇₃₅₆ =p ₁₇₃₅₆⊕λ₀ p ₃₃₉₀₉ =p ₃₃₉₀₉⊕λ₀ p ₃₆₈₃₃ =p ₃₆₈₃₃⊕λ₀where the addition ⊕ occurs in GF(2).

The subsequent L 1 information bits, that is, λ_(m), m=1, 2, . . . ,L−1, are accumulated at parity bit addresses that are calculated by thefollowing Equation 5:(x+m×Q ₁)mod M ₁ if x<M ₁M ₁+{(x−M ₁ +m×Q ₂)mod M ₂} if x≥M ₁  (5)where x denotes the addresses of parity bits corresponding to the firstinformation bit λ₀, that is, the addresses of the parity bits specifiedin the first row of the sequence of the Sequence Table, Q₁=M₁/L,Q₂=M₂/L, and L=360. Furthermore, Q₁ and Q₂ are defined in the followingTable 2. For example, for an LDPC code having a length of 64800 and acode rate of 5/15, M₁=1440, Q₁=4, M₂=41760, Q₂=116 and L=360, and thefollowing operations are performed on the second bit 2 using Equation 5:p ₂₂₅ =p ₂₂₅⊕λ₁ p ₁₀₁₅ =p ₁₀₁₅⊕λ₁ p ₁₂₂₂ =p ₁₂₂₂⊕λ₁ p ₄₄₁₅ =p ₄₄₁₅⊕λ₁ p₇₂₅₉ =p ₇₂₅₉⊕λ₁ p ₈₈₄₄ =p ₈₈₄₄⊕λ₁ p ₁₁₁₈₈ =p ₁₁₁₈₈⊕λ₁ p ₁₅₆₄₉ =p₁₅₆₄₉⊕λ₁ p ₁₇₄₇₂ =p ₁₇₄₇₂⊕λ₁ p ₃₄₀₂₅ =p ₃₄₀₂₅⊕λ₁ p ₃₆₉₄₉ =p ₃₆₉₄₉⊕λ₁

Table 2 illustrates the sizes of M₁, Q₁, M₂ and Q₂ of the designedQC-LDPC code:

TABLE 2 Sizes Code rate Length M₁ M₂ Q₁ Q₂ 5/15 64800 1440 41760 4 116

The addresses of parity bit accumulators for new 360 information bitsfrom λ_(L) to λ_(2L−1) are calculated and accumulated from Equation 5using the second row of the sequence.

In a similar manner, for all groups composed of new L information bits,the addresses of parity bit accumulators are calculated and accumulatedfrom Equation 5 using new rows of the sequence.

After all the information bits from λ₀ to λ_(K−1) have been exhausted,the operations of the following Equation 6 are sequentially performedfrom i=1:p _(i) =p _(i) ⊕p _(i−1) for i=0,1, . . . ,M ₁−1  (6)

Thereafter, when a parity interleaving operation, such as that of thefollowing Equation 7, is performed, parity bits corresponding to thedual diagonal matrix B are generated:λ_(K+L−t+s) =p _(Q) ₁ _(−s+t) for 0≤t<Q ₁  (7)

When the parity bits corresponding to the dual diagonal matrix B havebeen generated using K information bits λ₀, λ₁, . . . , λ_(K−1), paritybits corresponding to the identity matrix D are generated using the M₁generated parity bits λ_(K), λ_(K+1), . . . , λ_(K+M) ₁ ₌₁.

For all groups composed of L information bits from λ_(K) to λ_(K+M) ₁⁻¹, the addresses of parity bit accumulators are calculated using thenew rows (starting with a row immediately subsequent to the last rowused when the parity bits corresponding to the dual diagonal matrix Bhave been generated) of the sequence and Equation 5, and relatedoperations are performed.

When a parity interleaving operation, such as that of the followingEquation 8, is performed after all the information bits from λ_(K) toλ_(K+M) ₁ ⁻¹ have been exhausted, parity bits corresponding to theidentity matrix D are generated:λ_(K+M) ₁ _(+L−t+s) =p _(M) ₁ _(+Q) ₂ _(−s+t) for 0≤s<L, 0≤t<Q ₂  (8)

FIG. 4 is a diagram illustrating the bit groups of an LDPC codewordhaving a length of 64800.

Referring to FIG. 4, it can be seen that an LDPC codeword having alength of 64800 is divided into 180 bit groups (a 0th group to a 179thgroup).

In this case, 360 may be the parallel factor (PF) of the LDPC codeword.That is, since the PF is 360, the LDPC codeword having a length of 64800is divided into 180 bit groups, as illustrated in FIG. 4, and each ofthe bit groups includes 360 bits.

FIG. 5 is a diagram illustrating the bit groups of an LDPC codewordhaving a length of 16200.

Referring to FIG. 5, it can be seen that an LDPC codeword having alength of 16200 is divided into 45 bit groups (a 0th group to a 44thgroup).

In this case, 360 may be the parallel factor (PF) of the LDPC codeword.That is, since the PF is 360, the LDPC codeword having a length of 16200is divided into 45 bit groups, as illustrated in FIG. 5, and each of thebit groups includes 360 bits.

FIG. 6 is a diagram illustrating interleaving that is performed on a bitgroup basis in accordance with an interleaving sequence.

Referring to FIG. 6, it can be seen that interleaving is performed bychanging the order of bit groups by a designed interleaving sequence.

For example, it is assumed that an interleaving sequence for an LDPCcodeword having a length of 16200 is as follows:interleaving sequence={24 34 15 11 2 28 17 25 5 38 19 13 6 39 1 14 33 3729 12 42 31 30 32 36 40 26 35 44 4 16 8 20 43 21 7 0 18 23 3 10 41 9 2722}

Then, the order of the bit groups of the LDPC codeword illustrated inFIG. 4 is changed into that illustrated in FIG. 6 by the interleavingsequence.

That is, it can be seen that each of the LDPC codeword 610 and theinterleaved codeword 620 includes 45 bit groups, and it can be also seenthat, by the interleaving sequence, the 24th bit group of the LDPCcodeword 610 is changed into the 0th bit group of the interleaved LDPCcodeword 620, the 34th bit group of the LDPC codeword 610 is changedinto the 1st bit group of the interleaved LDPC codeword 620, the 15thbit group of the LDPC codeword 610 is changed into the 2nd bit group ofthe interleaved LDPC codeword 620, and the list bit group of the LDPCcodeword 610 is changed into the 3rd bit group of the interleaved LDPCcodeword 620, and the 2nd bit group of the LDPC codeword 610 is changedinto the 4th bit group of the interleaved LDPC codeword 620.

An LDPC codeword (u₀, u₁, . . . , u_(N) _(ldpc) ⁻¹) having a length ofN_(ldpc), is divided into N_(group)=N_(ldpc)/360 bit groups, as inEquation 9 below:X _(j) ={u _(k)|360×j≤k<360×(j+1), 0≤k<N _(ldpc)} for 0≤j<N_(group)  (9)where X_(j) is an j-th bit group, and each X_(j) is composed of 360bits.

The LDPC codeword divided into the bit groups is interleaved, as inEquation 10 below:Y _(j) =X _(π(j)) 0≤j≤N _(group)  (10)where Y_(j), is an interleaved j-th bit group, and π(j) is a permutationorder for bit group-based interleaving (bit group-unit interleaving).The permutation order corresponds to the interleaving sequence ofEquation 11 below:interleaving sequence={146 89 57 16 164 138 91 78 90 66 122 12 9 157 1468 112 128 74 45 28 87 158 56 61 168 18 161 95 99 139 22 65 130 166 118150 49 142 44 36 1 121 6 46 29 88 47 0 58 105 43 80 64 107 21 55 151 8145 163 7 98 123 17 11 153 136 52 3 13 34 160 102 125 114 152 84 32 9733 60 62 79 37 129 38 165 71 75 59 144 127 132 104 53 162 103 120 54 155116 48 77 76 73 113 119 179 177 41 19 92 109 31 143 178 108 39 140 10640 5 25 81 176 101 124 126 72 111 4 173 156 134 86 174 2 170 35 175 13715 24 69 96 30 117 67 171 149 169 63 23 20 167 27 147 51 10 82 131 85110 94 135 172 148 50 154 42 70 115 26 83 141 100 133 93 159}  (11)

That is, when each of the codeword and the interleaved codeword includes180 bit groups ranging from a 0th bit group to a 179th bit group, theinterleaving sequence of Equation 11 means that the 146th bit group ofthe codeword becomes the 0th bit group of the interleaved codeword, the89th bit group of the codeword becomes the 1st bit group of theinterleaved codeword, the 57th bit group of the codeword becomes the 2ndbit group of the interleaved codeword, the 16th bit group of thecodeword becomes the 3rd bit group of the interleaved codeword, . . . ,the 93th bit group of the codeword becomes the 178th bit group of theinterleaved codeword, and the 159th bit group of the codeword becomesthe 179th bit group of the interleaved codeword.

In particular, the interleaving sequence of Equation 11 has beenoptimized for a case where 4096-symbol mapping (NUC symbol mapping) isemployed and an LDPC coder having a length of 64800 and a code rate of5/15 is used.

FIG. 7 is a block diagram illustrating a bit interleaver according to anembodiment of the present invention.

Referring to FIG. 7, the bit interleaver according to the presentembodiment includes memories 710 and 730 and a processor 720.

The memory 710 stores an LDPC codeword having a length of 64800 and acode rate of 5/15.

The processor 720 generates an interleaved codeword by interleaving theLDPC codeword on a bit group basis corresponding to the parallel factorof the LDPC codeword.

In this case, the parallel factor may be 360. In this case, each of thebit groups may include 360 bits.

In this case, the LDPC codeword may be divided into 180 bit groups, asin Equation 9.

In this case, the interleaving may be performed using Equation 10 usingpermutation order.

In this case, the permutation order may correspond to the interleavingsequence represented by Equation 11.

The memory 730 provides the interleaved codeword to a modulator for4096-symbol mapping.

In this case, the modulator may be a symbol mapping device performingNUC (Non-Uniform Constellation) symbol mapping.

The memories 710 and 730 may correspond to various types of hardware forstoring a set of bits, and may correspond to a data structure, such asan array, a list, a stack, a queue or the like.

In this case, the memories 710 and 730 may not be physically separatedevices, but may correspond to different addresses of a physicallysingle device. That is, the memories 710 and 730 are not physicallydistinguished from each other, but are merely logically distinguishedfrom each other.

The error-correction coder 13 illustrated in FIG. 1 may be implementedin the same structure as in FIG. 7.

That is, the error-correction coder may include memories and aprocessor. In this case, the first memory is a memory that stores anLDPC codeword having a length of 64800 and a code rate of 5/15, and asecond memory is a memory that is initialized to 0.

The memories may correspond to λ_(i)(i=0, 1, . . . , N−1) and P_(j)(j=0,1, . . . , M₁+M₂−1), respectively.

The processor may generate an LDPC codeword corresponding to informationbits by performing accumulation with respect to the memory using asequence corresponding to a parity check matrix (PCM).

In this case, the accumulation may be performed at parity bit addressesthat are updated using the sequence of the above Sequence Table.

In this case, the LDPC codeword may include a systematic part λ₀, λ₁, .. . , λ_(K−1) corresponding to the information bits and having a lengthof 21600 (=K), a first parity part λ_(K), λ_(K+1), . . . , λ_(K+M) ₁ ⁻¹corresponding to a dual diagonal matrix included in the PCM and having alength of 1440 (=M₁=g), and a second parity part λ_(K+M) ₁ , λ_(K+M) ₁₊₁, . . . , λ_(K+M) ₁ _(+M) ₂ ⁻¹ corresponding to an identity matrixincluded in the PCM and having a length of 41760 (=M₂).

In this case, the sequence may have a number of rows equal to the sum(21600/360+1440/360=64) of a value obtained by dividing the length ofthe systematic part, that is, 21600, by a CPM size L corresponding tothe PCM, that is, 360, and a value obtained by dividing the length M₁ ofthe first parity part, that is, 1440, by 360.

As described above, the sequence may be represented by the aboveSequence Table.

In this case, the second memory may have a size corresponding to the sumM₁+M₂ of the length M₁ of the first parity part and the length M₂ of thesecond parity part.

In this case, the parity bit addresses may be updated based on theresults of comparing each x of the previous parity bit addresses,specified in respective rows of the sequence, with the length M₁ of thefirst parity part.

That is, the parity bit addresses may be updated using Equation 5. Inthis case, x may be the previous parity bit addresses, m may be aninformation bit index that is an integer larger than 0 and smaller thanL, L may be the CPM size of the PCM, Q₁ may be M₁/L, M₁ may be the sizeof the first parity part, Q₂ may be M₂/L, and M₂ may be the size of thesecond parity part.

In this case, it may be possible to perform the accumulation whilerepeatedly changing the rows of the sequence by the CPM size L (=360) ofthe PCM, as described above.

In this case, the first parity part λ_(K), λ_(K+1), . . . , λ_(K+M) ₁ ⁻¹may be generated by performing parity interleaving using the firstmemory and the second memory, as described in conjunction with Equation7.

In this case, the second parity part λ_(K+M) ₁ , λ_(K+M) ₁ ₊₁, . . . ,λ_(K+M) ₁ _(+M) ₂ ⁻¹ may be generated by performing parity interleavingusing the first memory and the second memory after generating the firstparity part λ_(K), λ_(K+1), . . . , λ_(K+M) ₁ ⁻¹ and then performing theaccumulation using the first parity part λ_(K), λ_(K+1), . . . , λ_(K+M)₁ ⁻¹ and the sequence, as described in conjunction with Equation 8.

FIG. 8 is an operation flowchart illustrating a bit interleaving methodaccording to an embodiment of the present invention.

Referring to FIG. 8, in the bit interleaving method according to thepresent embodiment, an LDPC codeword having a length of 64800 and a coderate of 5/15 is stored at step S810.

In this case, the LDPC codeword may be represented by (u₀, u₁, . . . ,u_(N) _(ldpc) ⁻¹) (where N_(ldpc) is 64800), and may be divided into 180bit groups each composed of 360 bits, as in Equation 9.

Furthermore, in the bit interleaving method according to the presentembodiment, an interleaved codeword is generated by interleaving theLDPC codeword on a bit group basis at step S820.

In this case, the size of the bit group may correspond to the parallelfactor of the LDPC codeword.

In this case, the interleaving may be performed using Equation 10 usingpermutation order.

In this case, the permutation order may correspond to the interleavingsequence represented by Equation 11.

In this case, the parallel factor may be 360, and each of the bit groupsmay include 360 bits.

In this case, the LDPC codeword may be divided into 180 bit groups, asin Equation 9.

Moreover, in the bit interleaving method according to the presentembodiment, the interleaved codeword is output to a modulator for4096-symbol mapping at step 830.

In accordance with at least one embodiment of the present invention,there is provided an intra-BICM bit interleaver that can effectivelydistribute burst errors occurring in a broadcasting system channel.

In accordance with at least one embodiment of the present invention,there is provided a bit interleaver that is optimized for an LDPC coderhaving a length of 64800 and a code rate of 5/15 and a modulatorperforming 4096-symbol mapping and, thus, can be applied tonext-generation broadcasting systems, such as ATSC 3.0.

Although the specific embodiments of the present invention have beendisclosed for illustrative purposes, those skilled in the art willappreciate that various modifications, additions and substitutions arepossible without departing from the scope and spirit of the invention asdisclosed in the accompanying claims.

What is claimed is:
 1. A broadcast signal transmission device,comprising: a first memory configured to store a low-density paritycheck (LDPC) codeword having a length of 64800 and a code rate of 5/15;a processor configured to generate an interleaved codeword byinterleaving the LDPC codeword on a bit group basis, the size of the bitgroup corresponding to a parallel factor of the LDPC codeword; a secondmemory configured to output the interleaved codeword; a modulatorconfigured to perform 4096-symbol mapping corresponding to theinterleaved codeword to generate a modulated signal; and an antennaconfigured to broadcast a transmission signal corresponding to themodulated signal over a broadcasting channel to a reception device,wherein the LDPC codeword is generated by performing accumulation atparity bit addresses which are updated using a predetermined sequence,wherein the interleaving is performed using the following equation usinga permutation order:Y _(j) =X _(π(j)) 0≤j<N _(group) where X_(π(j)) is a π(j)th bit group,Y_(j) is an interleaved j-th bit group, N_(group) is the number of bitgroups, and π(j) is the permutation order for bit group-basedinterleaving, wherein the permutation order corresponds to aninterleaving sequence, the interleaving sequence being for the LDPCcodeword having the length of 64800 and the code rate of 5/15 and beingrepresented by the following interleaving sequence: {146 89 57 16 164138 91 78 90 66 122 12 9 157 14 68 112 128 74 45 28 87 158 56 61 168 18161 95 99 139 22 65 130 166 118 150 49 142 44 36 1 121 6 46 29 88 47 058 105 43 80 64 107 21 55 151 8 145 163 7 98 123 17 11 153 136 52 3 1334 160 102 125 114 152 84 32 97 33 60 62 79 37 129 38 165 71 75 59 144127 132 104 53 162 103 120 54 155 116 48 77 76 73 113 119 179 177 41 1992 109 31 143 178 108 39 140 106 40 5 25 81 176 101 124 126 72 111 4 173156 134 86 174 2 170 35 175 137 15 24 69 96 30 117 67 171 149 169 63 2320 167 27 147 51 10 82 131 85 110 94 135 172 148 50 154 42 70 115 26 83141 100 133 93 159}, and wherein the interleaved codeword is generatedby the interleaving sequence on the bit group basis before performingthe 4096-symbol mapping so as to distribute burst errors occurring inthe transmission signal when the transmission signal is transmitted overthe broadcasting channel.
 2. The broadcast signal transmission device ofclaim 1, wherein the 4096-symbol mapping is a Non-Uniform Constellation(NUC) symbol mapping which corresponds to 4096 constellations.
 3. Thebroadcast signal transmission device of claim 2, wherein the parallelfactor is 360, and the bit group includes 360 bits.
 4. The broadcastsignal transmission device of claim 3, wherein the LDPC codeword isrepresented by (u₀, u₁, . . . , u_(N) _(ldpc) ⁻¹) (where N_(ldpc) is64800), and is divided into 180 bit groups each including 360 bits, asin the following equation:X _(j) ={u _(k)|360×j≤k≤360×(j+1), 0≤k<N _(ldpc)} for 0≤j<N _(group)where X_(j) is an j-th bit group, N_(ldpc) is 64800, and N_(group) is180.